Layer to Layer Spacing

[SpeedyG]

I hope you can help me with some laminate isuses that I cannot verify an answer for.

My problem is determining the layer to layer spacing between two 3oz planes using polymide material (4101/42).
These planes are common and +batt. The +batt plane can carry 310 volts. The existing design specified
a .004 mil minimum dielectric spacing between those two planes.

In IPC-2221, sec 6.3
...the minimum spacing between conductors, between conductive patterns, layer to layer conductive spaces
(z=axis), and between conductive materials...shall be in accordance with table 6-1.

Table 6-1 states that the spacings I would need, based on voltage on inner layers should be 0.25mm (.0098).

The material specification for the particular polymide material that we are using IPC-4101/42, states that the
Electric Strength, minimum is to be 2.90 x10^4 and the units are stated in volts/mm.

Given the material data sheet information...

a .004 dielectric should give me...
.004 x 25.4 = .1016mm
2.90 x 10000 = 29,000 Volts/mm
29,000 x.1016 = 2,946.4 Volts at .004 inch.

So... 4mils if quite plenty of isolation according to that. Even up to 2.9KV ?

If that is really true, what relationship does table 6-1 have to do with stackup thickness?

Thanks you for your time.

Regards,

Ralph A Gonzales, CID
Engineering Designer
L-3 Communications, Ocean Systems
818-833-2484

[Tom]

Ralph,

So you're with L-3 now. We're doing some designs for L-3 here in San Diego. Very interesting projects and I know what kind of technology you're up against.

There are two things that you can look at. You need a core material with a low dielectric constant and you need to have the manufacturer perform a "HIPOT Test".

Materials with a low dielectric constant are Polyimide and Cyanate Ester. These materials are also good for "High Speed Circuits". You could probably get away with a high Tg FR4 but I would run the HIPOT test.

Here's the fabrication note for the HIPOT test:
500VDC HIPOT test required on all buried capacitance images after etch. Final 500VDC HIPOT test required prior to packaging.

Here is the info on the HIPOT test and an explanation of your concern. A HIPOT (High Potentiometer) test checks thin dielectric for sparks. The manufacturer will charge the planes with 500 volts to detect sparking between them.

The copper on a piece of laminate has one smooth side and one ruff side. The ruff side is normally facing the core laminate (except in ZBC - Zycon Buried Capacitor material which is 0.05mm - 2 mil). The ruff side teeth are called "Dendrites". It's the dendrites that cause voltage sparking in the core material. If your board can pass a 500VDC it will certainly handle your 310-volt requirement.

You might also want to ask your manufacturer about the voltage specifications of ZBC. ZBC material has the dendrites turned away from the core and that's the secret on why they can have 2-mil core between planes.