Tom
04-07-2002, 09:04 PM
High-speed PCBs require a new approach
By Ken Tepper
EEdesign
March 4, 2002 (7:33 p.m. EST)
Electrical engineers, I regret to say: You no longer can assume the attitude of "Damn the torpedoes - full speed ahead!"
Translation: Given the speeds anticipated by current and emerging devices, it won't be long before board design will be impossible with today's traditional PCB design tools and methodologies. Like it or not, electrical engineers will have to get involved in some aspects of PCB design, with layout playing a less important role in the future.
Sound harsh? Not with FPGA speeds of several hundred megahertz, memory bus and networking speeds upwards of 1 GHz, and telecomm speeds of many gigahertz. If those lofty numbers don't faze you, recall that device edge rates - not necessarily clock speeds - are the main troublemakers in board design. Consequently, even a slower device on a design can trigger a high-speed problem. In fact, it takes only a 10-MHz signal to plop a board into the "high-speed troublemaker" category.
The way it works now is that electrical designers stay mainly in their logical world and, after entering a design and accompanying electrical constraints, fine-tune the design and constraints using simulation and verification tools. Engineers then pass the electrical design data and constraints to layout, where a separate set of designers translates the engineers' information into the physical world. After much back and forth, and several iterations later, the original goals may be realized and a prototype PCB produced.
That methodology is becoming obsolete. Sooner or later, rising board complexity and device speeds will team up to trash the schedule and slam the window on market opportunity. Face it, complexity is killing schematic entry as a way of life, and high speeds are forcing EEs into the physical world.
What's the way out? New tools and methods: a hardware description language, such as VHDL or Verilog, to enter the logic design; and software that can capture what the layout person knows, and give the electrical designer the ability to synthesize much of the PCB physical design based on that knowledge.
By "synthesis," I mean the ability to synthesize much of the PCB independently of the layout person. The synthesis must be based on constraints ranging from electrical to fabrication. Such constraint "templates" would be a company's "IP core" for PCB design and satisfy company requirements for PCB layout. Included would be electrical rules for parameters, such as length, EMI or crosstalk, and constraints for placement rules, such as component spacing, height restriction or rotation. Other constraint templates might include fabrication and testing requirements.
The more information about the physical world that can be pushed up front, the sooner the virtual prototype, and the sooner electrical designers can address the problems of the physical world. The ripest areas for synthesis treatment include developing layout constraints, component placement, and the routing itself. Verification also must move up to the EE's world.
Thus, the new breed of PCB design tool encompasses not just design entry or layout. It lets EEs take all project problems into account right at the start - from logic design to board design and fabrication, and beyond.
Ken Tepper is senior vice president of engineering and marketing for the product realization group at Innoveda Inc.
By Ken Tepper
EEdesign
March 4, 2002 (7:33 p.m. EST)
Electrical engineers, I regret to say: You no longer can assume the attitude of "Damn the torpedoes - full speed ahead!"
Translation: Given the speeds anticipated by current and emerging devices, it won't be long before board design will be impossible with today's traditional PCB design tools and methodologies. Like it or not, electrical engineers will have to get involved in some aspects of PCB design, with layout playing a less important role in the future.
Sound harsh? Not with FPGA speeds of several hundred megahertz, memory bus and networking speeds upwards of 1 GHz, and telecomm speeds of many gigahertz. If those lofty numbers don't faze you, recall that device edge rates - not necessarily clock speeds - are the main troublemakers in board design. Consequently, even a slower device on a design can trigger a high-speed problem. In fact, it takes only a 10-MHz signal to plop a board into the "high-speed troublemaker" category.
The way it works now is that electrical designers stay mainly in their logical world and, after entering a design and accompanying electrical constraints, fine-tune the design and constraints using simulation and verification tools. Engineers then pass the electrical design data and constraints to layout, where a separate set of designers translates the engineers' information into the physical world. After much back and forth, and several iterations later, the original goals may be realized and a prototype PCB produced.
That methodology is becoming obsolete. Sooner or later, rising board complexity and device speeds will team up to trash the schedule and slam the window on market opportunity. Face it, complexity is killing schematic entry as a way of life, and high speeds are forcing EEs into the physical world.
What's the way out? New tools and methods: a hardware description language, such as VHDL or Verilog, to enter the logic design; and software that can capture what the layout person knows, and give the electrical designer the ability to synthesize much of the PCB physical design based on that knowledge.
By "synthesis," I mean the ability to synthesize much of the PCB independently of the layout person. The synthesis must be based on constraints ranging from electrical to fabrication. Such constraint "templates" would be a company's "IP core" for PCB design and satisfy company requirements for PCB layout. Included would be electrical rules for parameters, such as length, EMI or crosstalk, and constraints for placement rules, such as component spacing, height restriction or rotation. Other constraint templates might include fabrication and testing requirements.
The more information about the physical world that can be pushed up front, the sooner the virtual prototype, and the sooner electrical designers can address the problems of the physical world. The ripest areas for synthesis treatment include developing layout constraints, component placement, and the routing itself. Verification also must move up to the EE's world.
Thus, the new breed of PCB design tool encompasses not just design entry or layout. It lets EEs take all project problems into account right at the start - from logic design to board design and fabrication, and beyond.
Ken Tepper is senior vice president of engineering and marketing for the product realization group at Innoveda Inc.