eo1668
03-11-2002, 08:40 PM
Hi,
1) I have this single layer pcb with two right angle 2mm pitch connector. I have create the pad size with round pad and pad size 20 mils larger than the drill size. During pilot run, the production discovered that after few time plugging in/out the wire harness, the solder joint start to crack and the connector become lose.
I have use this part lib for multiple layer pcb and don't seems to have this problem.
Is there any differrence in terms of pad design for single layer pcb and multiple layer pcb?
I was asked to change the pad to oval and enlarge the pad area as much as possible, is there any guide to this?
2) I have this 4-layer pcb, some of decoupling caps are placed at the bottom side of the IC close to the respective vcc/gnd pins. I have some disaggrement with the EMC testing guy in regards to the vcc/gnd via to the gnd and power plane.
He insist that I should lay the pcb such that the vcc/gnd pin from IC pins should go through via to the bottom side decoupling cap. This via should not go the gnd/power plane instead should pull out another trace from the decoupling cap through a new via and than to the vcc/gnd plane. Any one can share your experiences in regards to this?
Thanks in advance for all help.
Best regards,
Pl
1) I have this single layer pcb with two right angle 2mm pitch connector. I have create the pad size with round pad and pad size 20 mils larger than the drill size. During pilot run, the production discovered that after few time plugging in/out the wire harness, the solder joint start to crack and the connector become lose.
I have use this part lib for multiple layer pcb and don't seems to have this problem.
Is there any differrence in terms of pad design for single layer pcb and multiple layer pcb?
I was asked to change the pad to oval and enlarge the pad area as much as possible, is there any guide to this?
2) I have this 4-layer pcb, some of decoupling caps are placed at the bottom side of the IC close to the respective vcc/gnd pins. I have some disaggrement with the EMC testing guy in regards to the vcc/gnd via to the gnd and power plane.
He insist that I should lay the pcb such that the vcc/gnd pin from IC pins should go through via to the bottom side decoupling cap. This via should not go the gnd/power plane instead should pull out another trace from the decoupling cap through a new via and than to the vcc/gnd plane. Any one can share your experiences in regards to this?
Thanks in advance for all help.
Best regards,
Pl