Vias for .8mm BGA's and less

[sjm1027]

>*Currently our PCB designs utilize "encroached" solder mask via pads on
>pin escapes for all of our products.
>This was an adequate treatment for products with 1.27mm but as BGA lead
>pitch starts shrinking, the issue of adequate solder dams between ball
>pads and their pin escape vias becomes more problematic.
>Our standard pin escape via pad is typically .024" with .012" Finished
>Hole Size (FHS). Our requirement is solder mask encroached 1:1 with FHS.
>*First dilemma is that fabricators require .006" solder mask clearance
>over primary drill size.
>*This yields .001" solder mask encroachment on a .024" via pad with a
>.012" FHS under ideal conditions with no mask misregistration.
>*Problem becomes more pronounced with .8mm BGA pin escape vias. Our
>typical pad geometry for .8mm BGAs is .016". The pin escape via pad
>diameter for these devices is typically .018". That will yield only
>.005" clearance between the via pad and adjacent BGA pad. If
>fabricator requests .006" over primary drill, that leaves 0 solder mask
>on pin escape via pad with perfect solder mask registration. Problem is
>further exacerbated when fabricators increase solder mask apertures to
>accommodate misregistration and prevent solder mask from getting onto
>SMT pads. This results in as little as .003" solder dams.
>*Predict that there will be an abundance of issues whenever parts need
>to be reworked.
> Our preferred PCB surface finish is ENIG with SMOBC construction.
>*Typical practice in industry is to "tent" over vias with LPI. However,
>this practice is problematic and can lead to long-term PCB reliability
>issues.
>*Tenting vias with LPI solder mask will cause ENIG plating chemistry to
>become entrapped in vias.
>I would like to know how others are handling vias under BGA's with a
>pitch of .8mm or less.
>
>If we plug our vias we will have the following issues:
>
>*
> Via fill process will increase cost of PCB and will
>potentially increase lead time as well.
>*
> *Need to have vias covered with solder mask on BGA placement
>side to prevent potential for solder wicking onto via land. This
>becomes very critical during rework operations.
>
>*
> *Need to have vias exposed on non-placement side for test
>access.
>
>*
> *Vias filled with non-conductive media will cause probe
>contact issues during flying probe and In-circuit test.
>
>*
>Any help would be appreciated
>

[Skip Yutkus]

Sounds as though you just went thru a DFM analysis with one of the huge CEM's - do yourself a favor instead of talking to the guys in the cubicle, go to one of their assembly plants and look at a part they are currently building millions of, you'll see very little adherence to the draconian DFM guidlines - that appear to be put together by a committee of lawyers and "never worked in the factory" manufacturing engineers, you'll see LPI tented via's all over the boards they build, I personally have never seen a via with a 6 mil drill hole clearance on any production board "tent busters" yes, but not 6 mils.

Skip

If you find a solution let me know.

[Bubble]

recently just did a fpga with 9 mil pads and 20 mil spacing.

i used a 6 mil hole on a 12 mil via with 4 mil solder expansion.

the manufacturer we use, well we'll say isn't exactly top of the line, but adequate and they had no problems at all making this board.

even though those via's break most manufacturing rules.. hell its not even close to the minimum annular ring for testing purposes.. but it works and as long as u have at least one "test via" per net you're ok.

maybe another option is blind via's right on the pad. another no-no by manufacturers, but that's usually because its tricky for them to do. but again our manufacturer has pulled it off many times.

understanding the rules are more like guidlines to be followed for the most part is the best way to go. i think ur manufacturer is just trying to make it easier on themselves at ur expense.

[Skip Yutkus]

The problem here is, when these DFM reports are submitted, they include a dollar figure on how much more it will cost you if you don't adhere to their rules - management reads reports and does not listen to designers.

Skip