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View Full Version : Cadence Concept Design engg at Intel required


pat
06-15-2006, 08:08 AM
We are looking for a Cadence Concept Design Engineer for a 3-12 months contract position with Intel. Please send in your resume ASAP if interested or forward it to anyone you might think is interested

Assignment Information

Project Location: Hillsboro, OR - Hawthorn Farm 2

Project Name: DESIGN ENGINEER

Desired Start Date: ASAP

Length of Engagement: 3-12 MONTHS

Shift: 01

Necessary Skills (Must Have):
BSEE.

Experience in Power supply circuit design,
Cadence Concept schematic capture,
MS Office applications.

Additional Skills Desired (Nice to Have):

Experience in Cadence Allegro

PCB layout software,

Designs using PICs (ex. Microchip) with on-board firmware.

Project Description:

DE will support project to deploy a environmental stress tool (MST) within China HVM factories.

Daily Responsibilities:

Successful Candidate will be responsible for making on-going Schematic/PCB changes for new test equipment deployed in China high volume manufacturing of Intel motherboards. Additional responsibilities will include, validating changes on lab proto, documenting BOM changes and interfacing with external PCB vendors.