Simple Capture 9.2 bus question

[markrainess]

Need help with OrCAD Capture 9.2.446:

I have wires connected to a bus with net alias names such as: TDI, TDO, TMS,
TCK, RESET. At other points on the same bus I have wires connected which are
named with the same net alias names.

If I select one of these wires, right click, and do "highlight entire net", all
of the wires with the same net alias name become highlighted.

If I run DRC, I get warnings that these nets are not connected:

"WARNING: [DRC0034] Two wires/busses of different nets intersect visually, yet
nets are not connected RESET LHD Control Board, LHD Control Board Page 1
(13.10, 3.20)"

Reading about bus connections, I find that what I am trying to do does not seem possible.

I read that bus names and aliases must be named "busname[n...m]"

This seems to be telling me that I can only put signals on a bus which are of the form AD0...AD7.

Is this true. Is there no way to have a signal named RESET on a bus.

Please tell me how. I need to have this design finished by Feburary 7.

I will not be doing the layout.

Mark Rainess
mrainess@lhdvending.com
443-394-9522

[randychase]

Mark, as I understand it, you are correct that bus names must fall into that structure. In order to have a RESET for example, I would make it a separate line with an offsheet connector.

[markrainess]

I am trying to put these signals on a bus just to control the visual complexity of the schematic. It does not seem logical that there is no way to do this. Perhaps what I want is something that looks like a bus on paper but is not a bus to OrCAD.

I think of an address bus as consisting of the address lines and the control signals that are used to demultiplex them. Signals like ALE, RD, and WR do not have a numeric component. It does not seem right that OrCAD does not have some way for me to draw them visually as a bus. If they are all drawn individual as wires, the schematic is going to be very cluttered.

I do not want to run a separate line to every chip that needs the RESET signal.

Mark

[randychase]

I understand the intent you are trying to accomplish. I have never seen it doen where the mixed signals/control lines were included on the bus. And I do not think that Orcad supports doing it.

Most devices like this that I have seen on an Orcad schematic are drawn with separate Address and Data bus lines and then short stubs showing RESET, CLK, OE, etc.

[RLS]

CapFast by Phase 3 Logic has the function you describe. It is a type of bus but individual wire names are allowed. It is called a BUNDLE instead of a BUS. I'd typically use it for Bundling control signals (reset, Clk, DataIn, DataOut etc) as you suggest. I don't think Orcad Capture has this function.
RLS

[Skip Yutkus]

You don't have to run separate wires for your Jtag example - simply assigning the net name to the pin or a short wire stub will simplify your schematic.

Skip