PDA

View Full Version : Capture cis 15.1 netlisting problems


QingL.L
09-08-2004, 01:51 AM
Hi all

Design Name:
D:\hardware design\pxa255evb_1.dsn
Netlist Directory:
D:\HARDWARE DESIGN\ALLEGRO
Configuration File:
C:\Cadence\PSD_15.1\tools\capture\allegro.cfg

Spawning... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "D:\hardware design\pxa255evb_1.dsn" -n "D:\HARDWARE DESIGN\ALLEGRO" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "CONN SOCKET 4_FPC4-0.5_TOUCH PANEL" is renamed to "CONN SOCKET 4_FPC4-0.5_TOUCH PA".
#2 Warning [ALG0016] Part Name "COMPACT FLASH TYPE 2_0_CF1_COMPACT FLASH TYPE 2" is renamed to "COMPACT FLASH TYPE 2_0_CF1_COMP".
#3 Warning [ALG0016] Part Name "PHONEJACK STEREO_AUDIO_JK_PHONEJACK" is renamed to "PHONEJACK STEREO_AUDIO_JK_PHONE".
#4 Warning [ALG0016] Part Name "74LVCH16244_0_SSOP48_74LVCH16244" is renamed to "74LVCH16244_0_SSOP48_74LVCH1624".
#5 Warning [ALG0016] Part Name "74LVTH16245/SO_2_SSOP48_74LVTH16245/SO" is renamed to "74LVTH16245/SO_2_SSOP48_74LVTH1".
#6 Warning [ALG0016] Part Name "28F128J3A_TSOP_3_TSOP56_28F128J3A" is renamed to "28F128J3A_TSOP_3_TSOP56_28F128J".
#7 Warning [ALG0016] Part Name "ISPMACH4128_0_TSOP100_ISPMACH4128" is renamed to "ISPMACH4128_0_TSOP100_ISPMACH41".
Scanning netlist files ...
Loading... D:\HARDWARE DESIGN\ALLEGRO/pstchip.dat
Loading... D:\HARDWARE DESIGN\ALLEGRO/pstchip.dat
Loading... D:\HARDWARE DESIGN\ALLEGRO/pstxprt.dat
Loa
ding... D:\HARDWARE DESIGN\ALLEGRO/pstxnet.dat

Error: Line 980 in file D:\HARDWARE DESIGN\ALLEGRO/pstxnet.dat:
Reference designators inconsistent in xprt and xnet files
Detected in function: pstFindInstByOldPathName
Error: Line 980 in file D:\HARDWARE DESIGN\ALLEGRO/pstxnet.dat:
Error loading the net list file
Detected in function: ddbLoadPstXFiles
#8 Error [ALG0036] Unable to read logical netlist data.
Exiting... "C:\Cadence\PSD_15.1\tools\capture\pstswp.exe" -pst -d "D:\hardware design\pxa255evb_1.dsn" -n "D:\HARDWARE DESIGN\ALLEGRO" -c "C:\Cadence\PSD_15.1\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"


*** Done ***

Could anybody tell me why? (Section in red)
What's wrong with my design??

QingL.L
09-08-2004, 02:25 AM
The pst__.dat files