Part Outlines

[Tom]

Innoveda must fix the Part Outline issue.

Here are the issues:

Courtyards: We need an official Placement Courtyard layer. This is necessary for accurate pick and place machine data. We just can't guess how close we can place parts "On the Fly". Even the best designers need accurate Placement Courtyards to help them in the part placement phase.

PRO-E Interface: We need a layer dedicated to placing 1:1 scale Closed Polygons for PRO-E output. You cannot really use an Assembly Drawing layer because you want to illustrate Polarity Markers and other items. From what I understand is the the PRO-E interface only wants to see closed polygons and if you have anything else on that layer you do not get the results you expect.

Silkscreen Outline: What is the PowerPCB "Offical Layer" for placing silkscreen outlines? We use Layer_1.

[Lameris]

To be honest Tom, I can't figure out why this forums layer structure has so many silkscreen layers.

It gets to complicated for me. Then again, I believe in KISS.

I normally use TOP, everything else goes on Layer 26 or Layer 29.

[Tom]

The main reason why Layer_1 is used for Silkscreen outlines in because it is an electrical layer for running design rule checks. I can select Tools/Verify Design/Clearance (Options set to Body to Body & Outlines turned on) and get a complete DRC of my entire plart placement.

Putting "Everything Else" on Layer_26 or 29 does not provide DRC checking.

[petehouwen]

We are undertaking a project to rebuild our libraries. We have too many leftovers from as far back as PADS-2000. Some of the things we want to take advantage of are the PRO-E link, courtyards, and geometry.height. So far, these are the conventions:

Silkscreen outlines go on layer Top. Any Silkscreen information that we don't want to see all the time goes on Silkscreen Top. Moveable text (pin 1, polarity) markings are added as a label on Silkscreen Top, using the text entered in the "Silk" attribute.

Additional assembly drawing information goes on Assembly Drawing Top. Our AutoCAD conversion program looks here first, then on to Silkscreen Top.

Placement courtyards go on Layer 20. This is the layer that Pads uses when checking Placement Outline. Tall parts get an oversized courtyard to allow room for pick & place machines.

If the Placement courtyard isn't adequate, a closed polygon is added to layer 19 for PRO-E export. The PRO-E export can be instructed to look here first.

I have been playing with this on a test board, and it seems to work. The placement courtyards even make nudge partially useful (but still annoying) and checking is more correct. As soon as I can figure out how to get a padstack to understand thermal definitions, I'll go to town updating our library.

[Tom]

Everything that you mention regarding layer assignments is correct. One major lesson that we learned when starting a new library is metric. It seems that the entire EDA industry is going metric and if you're starting from scratch, do not build an inch based library or you will be rebuilding it again next year.

I never thought of placing the PRO-E outlines on Layer_19. That might be a good idea since all you really want is a 1:1 scale closed polygon of the physical part. No need for a reference designator and you cannot have any polarity markings or it will screw up the PRO-E data. PRO-E just wants a "Closed Polygon", that's it.

As far as Placement Courtyards, we just overhauled the pcbstandards library so that no courtyards touch each other in the placement. There could be a 0.05mm gap between courtyards. This allows the highest packing density and when you run Tools/Verify Design you can go to "Options" and turn on "Body to Body" and "Component Outlines" and you will get "NO ERRORS FOUND".

As far as modifying your "Custom Thermals", when you are in the Padstack Editor, select the "Inner Layer" line and then select the pull down menu "Pad Style" and then select Anti-Pad and that will set up your Plane Clearance. Then select Thermal and set up your ID, OD & Spoke Width. It works great and defining your own is way better than using the PowerPCB defaults.

I will attach a document that will help you setup correct padstacks, thermals and anti-pads.

[petehouwen]

I had considered going metric, but I am not rebuilding the libraries, just making sure each one has the new outlines and attributes. So I can't really justify the time required to go metric just yet (someday).

The courtyard sizes are just built to MMC. That way, I can set my clearance to 20 mils for dense designs, 60 to be more produceable. it's mostly just to make sure the board can be built, since I don't really use the courtyards for placement.

I did figure out the Thermal problem. I was just misreading the drop down box in the padstack setup. Now that I understand it, I am able to get some good CAMs.

Thanks for the info!

[Mark Larson]

Layer 20 seems to be the official courtyard layer, used to be called the nudge outline, but they have gradually changed "nudge" nomenclature to "courtyard".

Seems to me that maybe adding another outline layer is overkill, at most there should be a layer with the outline at MMC, another with assy outline, and another with silkscreen. I don't see the need for a "Pro/E" outline in addition to the MMC outline. Putting it on an electrical layer, I'd be real careful about that. You do not need to put an outline on L20 if you already have L1 at MMC and it is a closed polygon not a L shape. Verify design will check an outline on L1.

To cure the problem outlines cause in DFT Audit I am going to ask them to add a dialogue box indicating which layer your outlines are on (the MMC ones) This should be easy to do and would cure the problem of multiple outlines screwing up the audit if yo have TP's on the same side as comps.

[Tom]

I believe that if you have a Part Outline on Layer_1 at MMC & outside the solder pads that it would be overkill to add a Placement Courtyard to Layer_20. A good example of this is the Connector world. Most connector part outlines are drawn outside the pads and usually slightly larger than the actual part.

The perplexing thing is the PRO-E closed ploygon for 3D graphics. It seems that all PRO-E wants is a "Closed Polygon". Nothing else including Assembly Dots and Polarity Markings and other miscellaneous lines which you would normally draw on the Assembly Drawing layer. Also, the PRO-E outline should be as accurate as possible to the actual physical component for true scaling.

Also, we do need to resolve the DFT Audit errors we get when a "Test Point" falls on a Courtyard.

[petehouwen]

Pads checks shapes on layer 20 differently than other layers. Lines on Layer 20 are checked at 0 width. Any other layer includes the line width. So if you are checking 10 mil silkscreen outlines using 20 mil body to body spacing, you actually are checking at 30 mils. Not a real big deal. There will be parts that I do not add a courtyard, if the silkscreen is good enough. But the silkscreen and courtyard really do have different purposes. Silkscreen is a representation whose main purpose is to provide a convenient indication of a part's orientation on the board. A placement courtyard is an accurate identification of manufacturing requirements. Example: placing 1206s at 100 mil spacing. This is a valid spacing. Even 75 mils is OK. But the outlines, in order to not cover the pads, must be drawn at a size that will violate even a 0 mil spacing check. If I have a dense board and do not print a silkscreen, I can get a valid placement check, and a manufacturable board, using 100 mil spacing and layer 20 placement courtyards. The placement check takes solder pads into account, so I don't need to make the courtyard outside the pads, like I need to do with a silkscreen.

[petehouwen]

Oh, I forgot the testpoint thing.

Most of our boards lately have been low quantity prototypes, so I haven't used the DFT. What is the problem with DFT and courtyards?

[Tom]

When a test point falls on a placement courtyard on Layer_20, DFT Audit reacts as if Layer_20 courtyard is a "Part Body" line and produces an error marker on those test points.

This issue has gone back many years and I do not know why this has not been resolved. The only excuse Innoveda has is that the DFT Audit program was written by someone else other than PADS programmers and DFT Audit module could possibly still be owned by the creator who is unaware of the problem.

Innoveda just doesn't want to talk about it. At least all the people that I know of who have complained of this issue have not received a satisfactory response from Innoveda yet.

[Mark Larson]

DFT Audit considers any outline, whether it is on silkscreen, assy, courtyard, or L1. I can understand the problem, users use different layers for different purposes. Some users use L26 only, the cure would be for DFT Audit to allow you to specify which layer to use.

Part of the problem is that courtyard is a moving target, the courtyard size changes from company to company depending on their needs and assy & test equipment, and it will also change over time. It would be better in my opinion if the outline remained constant, make it at MMC and allow the user to adjust how much space they need around it via a clearance matrix box. Perhaps they could add an online DRC placement feature instead of that ridiculous nudge feature.

[petehouwen]

OK, I think I have figured out what the tespoint problem is. (But not how to fix it).

I missed the "Top Access" thing. We rarely test both sides. I don't have a real problem when I get an error for a testpoint on the courtyard. Here's why: My courtyards are not built for paper doll style grid placement. By setting my courtyard to MMC of the part, I can support any grid, and by checking palcement, not body-to-body clearances, I get a manufacturable placement, even gridless if I want (no I don't want). If I get a testpoint error because a top testpoint is on my courtyard, it means the testpoint is partially under a component, and not accessable. It's a valid error. I think that's why Pads checks that, they are trying to do the right thing. But, since my silkscreen outlines are often larger than the part itself, a testpoint on a silkscreen is NOT always an error.

Mark, you are correct. If I could tell Pads where my MMC outline was, I would get a reasonable testpoint report. Did you submit that one to pads?

[Lameris]

Q1: So Tom, are we making layer 19 the Pro E layer???

Q2: On SMT parts, should this layer include the leads which may be low profile with respect to the parts.

[Tom]

Gary,

We are discussing this issue at Wind River right now.

I also had a meeting with IPC (Dieter Berman & Gary Ferrari) regarding PRO-E output, because they currently do not cover this in the IPC-SM-782.

The reality of the subject is this - we were currently using The Assembly Drawing Layers for PRO-E output. But, those layers also contain Polarity Markings which apparently PRO-E does not like. Also, the Assembly Drawing data is not really 1:1 scale of the actual component because we intended to provide the assembly process with clean clear graphical data.

The PRO-E data should be a closed polygon on an isolated layer that represents the component size (true scale) that is used exclusively for 3D modeling.

Layer_19 is the only logical layer that I can think of to place this data, but we are still in the discussion mode. I.E.: Layer_19 is not locked in yet because the subject is currently in debate.

I will definitely keep everyone informed on the end solution via this thread and through public notification, like the listserver.

Since we do not own a copy of PRO-E to test this all out, I would very much like to work with you and to have you provide us the PRO-E parameters (The do's & don'ts). For instance the concept of adding the component leads to this new layer. What are the limitations? How do you add component leads that have various heights?

[Mark Larson]

Peter:

no, I have not submitted it officially as an enhancement request. I'd like to research it a little more. I believe the outline is considered if it is a closed poly, not open. So I guess that would be the workaround, have only the MMC outline be closed, every other outline open. But I am not completely sure that is true. Only have one license with DFT Audit, so it's sometimes difficult to find the time.

[petehouwen]

When PRO-E imports from PADS, it takes the boundries of your polygon and extrudes it to the dimension in the geometry.height attribute. If you include the leads, they will be extruded to the height of the component. That usually isn't necessary. When we need to define parts more accurately than just a box, we modify them in PRO-E and save them in a library. If part already exists, PRO-E will use that definition, rather than the information from PADS. The key is maintaining the part origin.

[Lameris]

Unless the lead is really unusual, like a TO-220 on its side, I don't usually include leads in the dimension.

I view the Pro-E tool as a good estimating tool for component heights and placement. It is also useful for positioning mounting holes and confirming board dimensions.

Because of this, capacitors, inductors, and connectors are critical components for loading the ProE outlines. IC's and chip resistors capacitors can usually be ignored in a design as they are usually low profile.