Generate netlist by Capture CIS Problem

[Prapat]

I have the problem with Capture CIS generate Netlist to allegro PCB design.
My schematics have two page if saparate generayt netlist it is O.K. no error detect but if I generate Netlist both page it still show error below.What is something wrong in schematic.

Design Name:
E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\mckinley_x1.dsn
Netlist Directory:
E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro
Configuration File:
C:\Cadence\PSD_15.0\tools\capture\allegro.cfg

Spawning... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\mckinley_x1.dsn" -n "E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"
#1 Warning [ALG0016] Part Name "CAPACITOR POL_1_0850_10U/16V,TANT" is renamed to "CAPACITOR POL_1_0850_10U/16V,TA".
#2 Warning [ALG0016] Part Name "CAPACITOR POL_1_C\SL170-B_10U/16V" is renamed to "CAPACITOR POL_1_C\SL170-B_10U/1".
#3 Warning [ALG0016] Part Name "CAPACITOR POL_1_C\S-TSC-B_4U7/16V,TANT" is renamed to "CAPACITOR POL_1_C\S-TSC-B_4U7/1".
#4 Warning [ALG0016] Part Name "CAPACITOR POL_1_C\S-TSC-B_10U/16V,TANT" is renamed to "CAPACITOR POL_1_C\S-TSC-B_10U/1".
#5 Warning [ALG0016] Part Name "CON1_3_FDUCIAL\40R_DNS\FDUCIAL\40R" is renamed to "CON1_3_FDUCIAL\40R_DNS\FDUCIAL\".
#6 Warning [ALG0016] Part Name "AM29LV800BB-70NS_0_SKT\TSOP48_AM29LV800BB-70NS" is renamed to "AM29LV800BB-70NS_0_SKT\TSOP48_A".
#7 Warning [ALG0016] Part Name "KM616V4002B-10NS_1_44-TSOP2-400F_KM616V4002B-10NS" is renamed to "KM616V4002B-10NS_1_44-TSOP2-400".
#8 Warning [ALG0016] Part Name "TDA1521_2_SOT110-1TDA1521_TDA1521" is renamed to "TDA1521_2_SOT110-1TDA1521_TDA15".
#9 Warning [ALG0016] Part Name "S558-5999-46_XFM
R\10/100BASET_XFMR,ETHER,100BS" is renamed to "S558-5999-46_XFMR\10/100BASET_X".
Scanning netlist files ...
Loading... E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstchip.dat
Loading... E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstchip.dat
Loading... E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstxprt.dat
Loading... E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstxnet.dat
Error: Line 660 in file E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstxnet.dat:
Could not create new pin inst <logicalPinName>
Detected in function: pstReadNodeSec
Error: Line 660 in file E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro/pstxnet.dat:
Error loading the net list file
Detected in function: ddbLoadPstXFiles
#10 Error [ALG0036] Unable to read logical netlist data.

Exiting... "C:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d "E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\mckinley_x1.dsn" -n "E:\PCB_Project_Design\Allegro\Project\SS542\Console\Schematic\allegro" -c "C:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "PCB Footprint"


*** Done ***

[cadpro2k]

It's a wild guess, since I can't see line 660 of the pstxnet.dat file, but I'd suspect you might have a signal name that won't fit the conventions of Allegro. Do the signal in Capture have spaces or slashes (i.e. / or # or @ or something?) or some incorrect character. If not, post line 660 of the file, and I'll have a look.

Good day.

Mitch