courtyards, nudges, and clearance rules

[Tom Frayda]

Tom-

I am experimenting in depth with nudge outlines/placement courtyards for the first time to determine if they are something that we would benefit from using here.

In PPCB 4.0, I have created a rectangular nudge outline on Layer 20 of a 1608 capacitor using a line width of 0.001mm and a clearance of 0.4mm from the edges of the pads. I have done the same for a through hole component with the clearance set relative to the component body and pads (still rectangular since I'm aware that PADS takes the bounding box approach for irregularly shaped components when performing a nudge).

The help screen for the clearance matrix suggests that SMD refers to surface mount component pads (ie: drill = 0) and that PAD refers to through hole component pads (ie: drill <> 0) and I have found this to hold true when performing design verification.

For test purposes, I set all clearance rule values to zero in order to examine each one at a time. What I've found indicates that there is a bug in the way PADS interprets SMD vs PAD clearance rules when performing a nudge.

PAD-PAD <> 0
nudges TH-TH as it should, but also nudges SM-TH and SM-SM

SMD-PAD <> 0
nudges SM-TH as it should, but also nudges TH-TH and SM-SM

SMD-SMD <> 0
nudges SM-SM as it should, but also nudges SM-TH and TH-TH

In other words, it appears that the nudge routine makes no distinction between SMD and PAD. This is unacceptable because I have situations where I want a larger SM-TH pad clearance than SM-SM pad or TH-TH pad.

If you can verify my findings, I will report it as a defect to PADS. Otherwise, please set me straight on where I'm going astray. Thanks.

+Tom

[Tom]

Tom,

I know that PowerPCB distinguishes between SMD & PAD, but I don't think that PowerPCB has a separate distinct "Nudge" factor built in. They are both identical. The reason why this slips through the cracks is because many designers never use the nudge feature.

There should be a menu dialog box where you can establish the nudge factor between SMD & PAD and for both top and bottom.

We just finished a high volumn production board and the distance between SMD and Through Hole devices on the bottom side was 3mm because of the "Selective Wave Solder" process. But the separation gap between the Top Side SMD to through hole was 1mm. Placement gets really critical in high volumn production.

Innoveda needs to address the entire issue of placement courtyards and nudge factors for both sides of the PC design layout. This is another "Wish List" item. It should be something that we have control over and can adjust. It's also really a part of DRC Checking because a misplaced SMD part on your board can mean the difference of a Rev Spin. No wonder why there isn't any great autoplacement program. There are no simple rule sets that we can currently establish.

Innoveda is aware that courtyards are being used by their customers on Layer_20, but their is no documentation on the subject, they don't talk about it and there is nothing in the software that you can control the level of DRC checking. So basically we have concluded that courtyards on Layer_20 are a visual placement aid until Innoveda addresses this issue.

If you call this in as a bug Innoveda will call it a feature enhancement request and add it to the list of over 600 other wish list items.