Decal Checker Software Program

[Tom]

We are introducing a new software program called the "Decal Checker". It currently checks for 60 different items and 17 more items are being added next week. The program is ready for download on pcbstandards.com in the Programs section.

Attached is a list of things that the program will check for once it's complete.

You need to export the libraries you want to be checked, the program accepts ASCII's only plus the ASCII files need to have the default extensions of .d and .p, but you'll only have specify the library name, you may omit the extension.

If your library parts match the standard library construction specification checklist (attached document) and can pass the "Decal Checker" program with "No Errors Found" then you can submit your part decal creations to the pcbstandards libraries and help put an end to "Duplication of Effort". You and I both know that we as an industry should only have to build something once that adheres to a good guideline and contribute our efforts for the common goal of creating a "One World Library" that is proven and passes all DRC, fabrication and assembly approvals.

The "Decal Contribution Program" starts January 1st, 2002. This expecially includes Molex and AMP Connector library parts. Please help us build the master PCB landpattern library to share for free with the rest of our fellow PCB designers. We can help each other increase our productivity or we can build everything from scratch and take twice as long. The solution is in your hands and your contributions.

Also, if you have a "Standard" part that is not in pcbstandards library, please send us the PDF file and let us build the library decal for you for free. Same day turnaround. We think that we already built all the standard parts in the world. So please let us know if we're missing one. The custom parts are for you to build and submit to us. Let's work together. Thanks!

[Mark Larson]

I haven't had the time to look, ao maybe you can tell me. are the pins for all parts placed on a grid? In the past I have found that placing pins on grid, and also rounding pads size to take full advantage of the grid was a big help in routing.

In the documentation for Rev 4 Innoveda recommends placing pins on grid, does this mean Blaze runs better if pins are placed on a grid?

One place I worked, parts were coded in both metric and inch, the worst possible scenereo in my opinion. Another codes in metric, but designs in inch. I haven't quite figured out the purpose for that unless it is that one day it is intended to jump to metric. In both cases grid is ignored.

Secondly is breakout, fanout in Padese, built into any parts? I have found that breakout in BGA's works better than not. In addition I am leaning heavily towards fannout built into other parts as well. Fine pitched parts, high pin count in particular. What's the first thing you do in the autorouter whether you are using Specctra or Blaze?

In 25 years of hand routing all manner of boards, including IC's, and using manny different autorouters including so called gridless routers I have found that placing pins on grid, placing parts so not to block channels, and in the case of SMD an ordered breakout pattern will contribute greatly to routing success.

On dense boards very few pins will be routed without vias, in the case of high pincount fine pitched parts 99.5% of pins will have a via, so why not build the fanout in right, and you'll never have to consider it again. Perhaps parts can be built with alternate decals, one with breakout and one without. Perhaps alternate breakout pattern could be put in as alternate decals as well.

[Tom]

Mark,

Let me answer your questions one by one......

1. All pin pitches to all parts are exactly what the manufacturer specifies as the "Lead Pitch". The Lead span and pad length however can be tweeked to achieve the best routing results and still maintain excellent solderability.

I really don't know that much about the Blazerouter and placing pins on a grid to accomodate Blaze, but I do know that there is a metric standard that all the standard groups are trying push forward and that is that all future components that are truly metric by design will have all the pin origins snap to a 0.05mm grid system. All hole sizes are in 0.05mm increments and all pad sizes are in 0.05mm increments.

2. Building Via Fannouts directly into library parts in PowerPCB is a major hassle and makes the part four times larger. Once we spent months on a CALAY System building in all the via fannouts because CALAY had "Pin Association" which was a great library feature. You could insert two pads and then rename them both to "PIN 1". Then tie them together with a copper path and the router acknowledged both pins as a routing point. The results were disastrous with double sided placements. We basically tied our hands behind our backs and could not optimize the placement of bypass caps, terminating resistors, crystals and other critical parts.

We spent four months of building a complete SMT library with full fannout thinking that it was going to increase our productivity and it actually worked against our productivity. Also, not every pin on every device was in the net list, but every part had a complete fannout which took up valuable real-estate and you could not move or delete the unused vias. After trying the new library on a dozen boards we realized that it just doesn't work. And we thought that maybe someday there would be an autorouter that would automatically fannout part pins 100% fast and accurate.

We do not build vias into the parts because of the above reasons, but most of all because PowerPCB software does not have this feature. Sure you can create workarounds, but Innoveda really needs to add a feature in the Decal Editor called "Pin Association" where you can insert two or more pins and associate them together to become one pin. It is a royal pain in the ass to take a 600 pin BGA and place 600 Copper Circles and 600 Copper Paths and associate them with 600 pads. Then you also have to be concerned that some of those pins are soldermasked over and some have to be used as test points. What a nightmare that turns into. If you want to add vias in your library decals, this should be added to the PowerPCB "Wish List".

In closing, we (all the people who have contributed to the development of the pcbstandards library) feel that we have created the ultimate library with full flexability. If anyone can recommend or suggest how we can improve the library, we would like to hear those comments.

[Mark Larson]

Sometimes history goes full circle.

How do you fannout a BGA? If vias go out from under the part, you loose allot of space.

[Tom]

It is very important to fanout a BGA in quadrants. Fanout the upper left quadrant up & to the left. Fanout the upper right quadrant up & to the right. So on and so forth. This will leave a large path in the shape of a cross under your BGA to place Bypass Capacitors on the opposite side and it will allow a suffient Power & GND path to enter the center of the BGA.

Engineers or rather Test Facilities or Assembly Shops that perform board testing normally want all unused BGA pins to be fanned out to a Test Point. This is very important for them to debug a possible Solder Bridge error. PowerPCB really needs a new feature here called "Single Pin Nets" so that these unused BGA pins can have their own netname. The BGA Test Points absolutely need to be solder masked over on the BGA side and exposed on the opposite side. The regular vias can be soldermasked over on both sides.

If you fanout a BGA in the Decal Editor, you lose total control over which via is a regular via and which one is a Test Point for Solder Mask coverage & exposure.

On very dense boards we try to route as many traces out of the BGA, on the layer that the BGA is on, as to avoid putting vias under the BGA.

[randychase]

It is my take that I would rather not have fanouts on most of my parts. I do use them some times, and I have a few parts that are pre-fanned out, but I consider those the exception.

But the BGAs...maybe. They are kinda a different animal.

[Mark Larson]

It seems you both agree with me, sort of, that it may be good to fannout BGA's. I do the quadrant fannout.

I let DFT Audit take care of the single pin nets, have it insert a via outside the board outline, then if it's a BGA pin that does not have another pin flagged as a test point immediately adjacent I turn on that pins test flag manually and delete the added test point. This pretty much takes care of all single pin nets for ICT.

In CAM I process the SM layer with test points, that way only the vias that I'm using for test are left uncovered.

If the BGA is 1.27 pitch and ICT test nodes on 1.27 centers are acceptable, you've got ICT and fannout covered all within the part. I fail to see why you would want to bring vias out from under the BGA on dense boards, that only eats up real estate.

There are some shortcuts to saving time when building BGA's, nuild one pin step and repeat, rotate the pin step and repeat, ... also import alpha nyumerics.

Would be nice if they'd improve the decal wizard.

Take a look at the attached pcb file, it shows a 240 QFP with some 0603 & 0805 on bottom side. An example of another type of part that may benefit from predefined fannout.

[Tom]

Mark,

I believe there is a definite advantage to having a dual library, one fanned out and one not fanned out so you can pick and choose what's best for your application. But, PowerPCB really needs to improve the Decal Editor to make the fanout process "Legal" and easy to create.

Also, I downloaded your attachment and checked it out. Looks good. Watch out for one thing and that is "Creating a Plane Wall Barrier". Your via fanout is spaced so that you can get one trace between them, but the Anti-pads on the plane layer overlap. This prevents a clean return path for all the traces that run in-between these vias. Always place your vias where you have at least a minimum 0.1mm gap between the plane anti-pads.

[Mark Larson]

I'm using S/M and my settings result in .125 between vias, using CAM planes and .635 over drill results in half that so it would etch away. I've found that once you get to a .65mm pitch part, you have to be inventive to meet DFM. In my .65 BGA's I have built in fannout vias that are oval and change orientation with routing direction. Manually putting them in with teardropping would achieve the same thing.

[Mark Larson]

BTW, I'm not trying to get people to change the way they build their parts & Lib, just trying to get feed back on what I'm doing or would like to do.

I have found that if all pads in a BGA can be ascaped to the outside of the part, it may be a good idea not to build in fannout, here's why:

On the fine pitched parts, if you build in fannout you are tying your hands because to get the vias in they have to be smaller than most shops can build with common IPC accepted standards. On a .65mm pitch BGA I have found that the maximum via pad size you can squeeze between the ball pads is 20 mils. Since the lowest drill most shops can go down to without cost increase is 10, you are really pinching their throughput, very little annular ring even with teardropping you are going to get breakout. So if you can escaps all pads to the outside you can use larger vias. Even using 4 mil line and space only the smallest of BGA's can you do this. A 9x9 can be done but I believe a 10x10 can only be done if you are not using 100% of the pins and don't have to probe unused pins. Most shops consider 4/4 cost+, so you'll have to go 4/5 or 5/5 and the max BGA size is even smaller, 7x7 or 8x8 if not all pins used.

In fact I've found the .65mm part to be the transition point where so called standard board fab processes changes. If your board is predominately that size or smaller, you are pretty much forced to go away from standard drilled through via technology. If you have only a couple of these parts, forsight is required including perhaps finding an alternative part if one is available.

[petehouwen]

I have been perusing the Decal checklist. As I have mentioned earlier, we are rebuilding our libraries, so I am trying to make sure I include all improvements. Unfortunately, we haven't gotten approval to move to all metric :( so the PCB checker will not help me. But I do have a few questions:

Padstacks:
Why include solder and paste masks? Isn't there more flexibility in using the CAM functions for this?
Why no thermal definitions for Layer 25? These are required to output RS274X properly.
Why keepouts for non=plated holes? Design rules already allow hole to anything checking, so isn't this redundant?
Text:
Why Left/Center justification?
Courtyard:
Why .3mm from pads? Courtyards can be placed across pads with no problem. Spacing checks and placement violations (even nudge, for all that's worth) check courtyards and pads, so courtyards can ignore pads and define only body size.
Landpattern origin:
Doesn't adding an additional geometry on the courtyard layer make pads ignore the closed polygon on that layer? Or is that a ProE export consideration only?
Decal and Part-Type name must match:
What about multiple parts using the same decal?
Part type General, connnector box
Just a suggestion - some connectors are more easily described on the schematic as a single part, rather than a connector. (i.e., high pin count headers) We create 2 Part Types, 1 as a connector, with individual gates, and 1 as a part, with a single decal with multiple pins.

Just trying to learn the reasoning behind some of these, before I get too far into my library.

Also, I have a visual basic script that I use for updating my decals. It adds courtyards, ProE outlines, silkscreen labels, geometry.height attributes, (all if requested). It also reorients and justifies Ref Des labels, checks for text on silkscreen layers and prompts to change these to labels. It checks and warns (but doesn't revise) lines with non-standard width or on non-standard layers. It does work for mils or metric (don't tell my boss). Inches require additional user input, but who uses them anyway. I'm still not comfortable distributing it, because I'm not sure I've uncovered all of the bugs. But when it's ready, I'll post it.

Pete

[phillipr]

The best way to find bugs in software is to let it out into the big wide world.
works for innoveda. :)

[Tom]

Pete,

First of all I'm sorry to hear that you cannot design in metric units. Your company obviously is not listening to any of the worlds standards organizations - NIST, ANSI, IEC, IPC, JEDEC, EIA and all the rest. What you are doing is wasting your time in the English units because all future machine automation will be in metric units. See www.nist.gov/metric

Question: Why include solder and paste masks?

Answer: The pcbstandards library is not just for PowerPCB. All other CAD Tools use full padstacks. It provides the PCB Designer with much more flexibility and creativity than "Global Oversizing".

Question: Why no thermal definitions for Layer 25?

Answer: When you use Layer_25 to create CAM Planes, PowerPCB automaticatically uses the OD of the value to create the Anti-pad and the Thermal Relief. If you want to use "Custom Thermals" you must modidify the "Inner Layer" pad to define your thermal.

Question: Why keepouts for non=plated holes?

Answer: Because some of your designs are 0.1mm Trace / Space, some are 0.15mm Trace / Space, some are 0.2mm Trace / Space, but you always want to keep all copper pour, traces and pads a minimum 0.3mm away from all non-plated holes.

Question: Ref Des - Why Left/Center justification?

Answer: First it's Centered so you can easiliy work with a "Full Screen Cursor" to line up the ref des with the part. Second, it's on the left when you place the ref des on the right side of the part so that when the ref des changes in length (no of characters) it will not interfere with the part. when you place the ref des on the left side of the part you rotate the ref des so that the origin is on the right side of the ref des. When the red des grows, it grows to the left and does not interfere with the part.

Question: Why are Courtyards .3mm from pads?

Answer: Courtyards are placed in 3 different locations for the 3-Tier library system. For the Least Library they are 0.05mm away from the pads. For the Nominal Library they are 0.25mm away from the pads and for the Maximum Library they are 0.5mm away from the pads. This way you can set your Body to Body clearance for 0.05mm, place all your parts and "Do Not touch or Overlap" any courtyards and run a full DRC Clearance Check on Body to Body and Outlines and have "No Errors Found".

Question: Landpattern origin: Doesn't adding an additional geometry on the courtyard layer make pads ignore the closed polygon on that layer? Or is that a ProE export consideration only?

Answer: We've been adding a crosshair on Layer_20 with the courtyard for the past 10 years. Never had any problems. Also, Layer_20 is not used for PRO-E output. Layer_27 is currently used for that, however we are trying to convince Innoveda to dedicate a layer for PRO-E output.

Question: Decal and Part-Type name must match: What about multiple parts using the same decal?

Answer: pcbstandards has a MISC library that has manufacturers part numbers for the Part-Type that points to a standard decal. This is extremely popular with SOT-23 packages where the pin assignments are: Source, Gate, Drain, Anode, Cathode, Collector, Emitter, Base, etc.

Your library utility program sounds like it would automate some library construction activity. Please let us know when it's ready. We'll definitely use it.

[petehouwen]

Thanks, Tom

That pretty much answers my questions.

I didn't realize that the libraries were created for multiple platforms. I guess I've got my Pads blinders on.

The courtyard question wasn't so much a concern about the dimension, but more why are pads involved in the courtyard. (back in the day) When courtyards were used for paper doll placement on a grid, they needed to be boxes. But now that they are used for placement clearances for any grid (even gridless), they should really mimic the actual part, and use the design rules to set body to body and pad to pad clearances.


This forum has been very helpful in getting my libraries together. Thanks, all.

I may add some annotations to the program (in case it needs to be modified) and email it out to a few people willing to crash their systems finding bugs. (I did mange to fix that pesky 'Segmentation Fault' bug)