Space violation checking in 4.0

[nnewman]

I just posted a problem in 4.0 for Innoveda (case 11000) referencing space violations using body to body checks and placement outline checks. Checking body to body my test board had 18 errors, checking placement outlines it had no errors, checking both body to body and placement outlines it had 196 errors.
I would be interested in finding out if any one can duplicate my problem.
My reason for writing here is that after researching nudge checks (in 4.0 its called placement outlines) I found out that layer 120 is now the designated coutryard layer (expanded layers and .ayer 20 unexpanded). The suggested layer structure for 4.0 has 63 and 64 as the courtyard layers. It appears that only one layer 20/120 can be courtyard layer.

[Tom]

Layer 20 (120) is the current layer for placement courtyards.

This subject is driving me crazy too because I thought that if you set the Body to Body Design Rule to 0 (Zero) that you could bump courtyards but not overlap them and get a clean DRC check.

I am thinking about moving all courtyards inward by 0.05mm to avoid the DRC errors, but I don't know if the real problem is with the software.

I will make a call to tech support and see what their suggestions are.

One other problem that is coming up with courtyards is DFT Audit. It seems that DFT Audit looks at the courtyard the same as a silkscreen outline. DFT Audit produces an error when a test point is on a silkscreen outline. If a test point is on a courtyard, the same error message occurs.

Innoveda needs to acknowlege that courtyards are a necessary part of library construction and that they have a useful purpose in the part placement phase.

[nnewman]

I just got a phone call from Innoveda support. Checking using Placement outline can not be done without body to body checking on. Bug report # 16753.

[Tom]

Nick,

Thanks for the update. If you send me an e-mail I will send you a list of compiled PowerPCB V4.0 bugs so that you can elaborate on what Innoveda is doing to fix this problem.

[ltrakal]

i have a stupid question but what happend if i have a component without placement outline? i have a lot of coils made in the pcb adn stuff that is done before in ads agilent and i import that into pads via dxf, these components have od shapes, so should i make a placement outline?

[Tom]

Placement Courtyards are primarily used for parts that have the silkscreen outlines on the "Inside" of the pad pattern. If the silkscreen outline is on the "Outside" of the pad pattern, a Placement Courtyard is not necessary if you use good PCB design techniques and leave adequate space between components.

Placement Courtyards are only a guide to use to acheive a part placement that can be successfully machine placed using pick & place equipment.

We just removed the Placement Courtyards from over 6,000 connectors in the pcbstandards library because 99% of them have silkscreen outlines on the outside of the pins and because most of them need to be hand assembled.

Courtyards are an invention of IPC standards for good placement boundaries for pick and place machines. You need placement courtyards on QFP's and SOIC's and Chip Resistors & Capacitors to use as a guide to aid the assembly process. But, this is primarily due to the fact that the QFP & SOIC silkscreen outlines are made on the inside of the pins. If the silkscreen was made outside the pins you would not need Placement Courtyards.

The reason why parts have silkscreen outlines on the inside of the pins is to leave room outside the pins for the reference designators.

[ltrakal]

ok thanks, i don't have even silkscreen in this coils, but i asked that because i thought we need that for drc check, but id the component is not clearly interfering any other one it should be fine so..

thanks

[Tom]

If you do not have silkscreen on your components, then you should have Placement Courtyards on Layer_20 to illustrate the component placement boundaries. This will check for DRC errors.