Dielectric properties of internal layers?

[jdupre]

Can someone tell me what sort of isolation I can expect between trace spaces on internal layers of a FR-4 board?

I am concerned about ESD coming in on some through-hole connectors and "jumping" to inner-layer traces that need to snake inbetween the through-hole pins.

With internal spaces of ~12 mil (.3mm) should I even worry about it?

Thanks,

- Joe

[Tom]

Joe,

A trace that passes by a via or a through hole pin does not cause crosstalk or EMI issues. It's when two traces travel parallel for a distance (depending on the frequency of the signal) that cause crosstalk.

The trace / space clearance is the secret. If you have a 0.5mm (20 mil) trace and a 0.3mm (12 mil) space, that's not good because the waveform of the 0.5mm trace will encroach on the neighboring trace. Most designs have the same trace width and trace space (Trace Width = Trace Space).

When you make the trace space twice as big as the trace width you reduce cross talk by a factor of 4 times.

Anyway, I don't see anything in your situation that will cause EMI problems unless the traces going through the connector pins are Audio or Video signals (critical nets) that have no relationship with the connector.

Rule of thumb - Never route critical signals near a connector that has nothing to with the critical signals. If you do, this will cause EMI problems and you will spin Rev B to either move the connector or move the traces.

[jdupre]

Tom,

Thanks for the reply, but I was speaking of Electro-Static Discharge, not EMI.

I found this link that did testing on a 4 layer board to test compliance of different spaces to "GR-1089-CORE":

http://www.ce-mag.com/archive/03/01/hilliard.html

Their testing was only up to 2500V however, and I thought that human-generated static charges could get up to 16,000v. Lightning is another thing alltogether, and I don't think I want to go there.

- Joe

[robert Tarzwell]

FR4 has a initial rating of 1000 volts per mil with a degrated aged real life rating of 300 to 600 volts per mil. There will be a laminated joint between inner layers which could have some micro voids, which will lower silightly the voltage rating. One major area to worry about is the size of the migration of the elctroless copper in the holes and vias. the copper can and does leach out into the lamiante up to 1-2 mils. However all said and done your spacing of 12 mils is somewhat large so you will probibly be ok, it all depends on the rise time/voltage of the signials. and there spacing and lenght they travel together.